This page gives the implementation details for the design problem on image compression.
Interface
Both the input bitstream and the output image will be interfaced through separate memory subsystems.
The bitstream, which is composed of 14-bit symbols representing run-encoded sections of the image, will be stored in the bitstream memory (BMEM). Data from BMEM will be transferred in 14-bit words (bdata), with the decoder issuing a 16-bit word address (baddr) to BMEM. A behavioral model of BMEM will be provided during checking, but you may have to build your own models for your preliminary testing. Take note that BMEM is not clocked: once baddr is issued, bdata is immediately released. Contents of bmem can be generated from the MATLAB model of the image compression algorithm.
The decoded image will be stored in another memory, which we will refer to as image memory (IMEM). IMEM will contain 2^16 8-bit words, addressed by 16-bit address iaddr. Pixel information, which is represented in 8-bit data (idata), is written to IMEM using a write enable signal, iwr. Unlike BMEM, IMEM must be clocked. A behavioral model of IMEM will be provided during checking, but you may have to build your own models for your testing.
Aside from the memory interfaces, the only other ports of the decoder are the clock (clk), low-asserted reset (nrst), and high-asserted done signal. The decoder must be free-running: as soon as the nrst is de-asserted, the decoding process begins. Upon completely writing all pixels to IMEM, the done signal is asserted to signify that decoding is complete.
Deliverables
The decoder must be implemented using a generic 90nm CMOS process. At the minimum, designs must be synthesized.
Each major process in decoding will merit points. The distribution of points and details for each are:
- 20% – Run-length decoding: completely decode an 8×8 block (Y_zig_dec).
- 10% – Reverse zig-zag scan: completely produce quantized QCIF image (Y_q_dec). Half points if process is performed on 8×8 block only.
- 20% – Inverse quantization: completely produce DCT QCIF image (Y_iq). Half points if process is performed on 8×8 block only.
- 30% – Inverse DCT: completely produce normalized decoded image (Y_dec_norm). Half points if process is performed on 8×8 block only.
- 5% – Complete image decoding: completely produce decoded image in correct scale (0-255).
- 5% – Incentive for smallest area: 5% goes to the design with smallest area, 0% to the biggest area. Linearly distributed.
- 5% – Incentive for fastest logic: 5% goes to the design with highest maximum clock frequency, 0% to the lowest. Linearly distributed.
- 5% – Complete design layout: applicable only to those who have complete image decoding.
The bullets shown above are ladderized: in order to score the next bullet, you must be able to implement the previous one (perform the process on the 8×8 block level, or earn at least half of the points of the previous bullet). Take note that you do not need to perform each process for the whole QCIF image before moving on to the next one, since each 8×8 block is independent from one.
Points for the incentive 10% can only be achieved when complete image decoding is implemented.
Verification
Complete image decoding is the easiest process to verify since the values of the output are integers. In cases where the values are non-integers, you may use the internal number representation (determined by you) for representing the output. Just make sure to provide the necessary transformation (MATLAB code or something similar) when you have your design checked. Operations used for the transformation are limited to non-matrix operations. You will also be the one to provide the program or function that automatically transfers/forwards VCS outputs to MATLAB for verification purposes of partial designs.