Graduate (MS and PhD) Alumni

2021

  • John Jairus D. Eslit (MS EE 2021), “Design, Fabrication, and Modeling of a High-Contrast Grating (HCG) MEMS-tunable Vertical Cavity Surface Emitting Laser (VCSEL) for Optical Interconnects“
  • Ian Christian Fernandez (MS EE 2021), “An Energy-Efficient Temperature to Digital Converter Using CMOS Thyristors and a Subranging Time-to-Digital Converter“
  • Michael G. de los Reyes (MS EE 2021), “Analysis and Evaluation of Vibration-Type Detector as an Enabler to the SSHI/SECE Reconfigurable Interface“

2020

  • Ryan Albert G. Antonio (MS EE 2020), “Post-training Bit-selection Control for Energy-Efficient Hyperdimensional Computing Architecture“
  • Alexis Czezar C. Torreno (MS EE 2020), “Power and Area Oriented Implementations of Lightweight Cryptographic Algorithms for FPGA-based Wireless Sensor Networks“
  • Jean Marriz M. Manzano (MS EE 2020), “Investigation of Surface Roughness Effects on Piezoelectric Cantilever MEMS-Based Energy Harvesters“

2019

  • Mark Daniel D. Alea (MS EE 2019), “Load Current Cancellation using PMOS Replicas and Digital Feedback for Temperature Coefficient Reduction in Ultra-Low Power Voltage References“
  • Patrice Abbie D. Legaspi (MS EE 2019), “Input Power Range Extension using Duty-Cycling and Granularity Reduction in a 5.8 GHz RF Energy Harvester Dynamic Matching Circuit”

2018

  • Christopher G. Santos (MS EE 2018), “Optimal Oversampling Using Probabilistic Error Modeling in Low-Power Digital Energy Detection Receivers“

2017

  • Aristotle D. Lopez (MS EE 2017), “MPPT-Controlled Adaptive Reconfigurable 5.8GHz RF Energy Harvesting Front-End to Extend Operating Range“
  • Frederick Ray I. Gomez (MS EE 2017), “A Study of Active Balun Circuits for WiMAX Receiver Front-End Using a Standard 90nm CMOS Process“

2015

  • Rico Jossel M. Maestro (MS EE 2015), “A Resilient Temperature Sensor System for Power Line Monitoring in 65nm CMOS Process“

2014

  • Bernard Raymond D. Pelayo (MS EE 2014), “Design Methodology for Process and Temperature Resilience of Switched-Capacitor Regulators for Power Line Harvesting Applications“
  • Sherry Joy Alvionne V. Sebastian (MS EE 2014), “PVT-Aware Digital Techniques for Low-Power, 0.5V, On-Chip Processing Unit for the SmartWire Node in 65nm CMOS Process“
  • Joana Rochelle R. Ortiz (MS EE 2014), “An Integration-Biased BER-Aware Design Methodology of a BPSK Analog Transceiver Front-End for Power Line Sensor Nodes“
  • Adelson N. Chua (MS EE 2014), “BER-aware, PVT-resilient, All-digital BPSK Demodulator for Energy Harvesting sensor Nodes“
  • Kristoffer M. Monisit (MS EE 2014), “An Energy Harvesting Module for a 23kV Distribution Line Sensor Node in 65nm CMOS“
  • Renan C. Nuestro (MS EE 2014), “Integration Based LDO Design in Power Line Energy Harvested Sensor Nodes“

2013

  • Anne Lorraine S. Luna (MS EE 2013), “A Method for Timing Closure in Supply Voltage Scaled CMOS Digital Circuits with Dual Vth Devices“
  • Joseph Bernard A. Constantino (MS EE 2013), “A 0.5V BPSK Narrowband PLC Transceiver Analog Front End for Smart Current Sensing of High Voltage Lines“
  • Darryl Aldrin M. Dioquino (MS EE 2013), “Less-reused Filtering and Live Time Prediction in Multi-core Processors With A Shared L2 Cache“
  • Mark Gerard T. delos Reyes (MS EE 2013), “RF Energy Harvesting Systems for Autonomous Wireless Sensor Networks“
  • Sherlyn C. dela Cruz (MS EE 2013), “1.2-V 5.8-GHz 90nm CMOS RF Power Amplifier Parameter Enhancement Techniques“
  • Hearty Z. Abadies (MS EE 2013), “Effects of Integrated Controller Techniques on the Performance of Flash Memories“
  • Chris Vincent J. Densing (MS EE 2013), “H.264/AVC Decoder Interprediction Cache Architectures“

2010

  • Dean Michael B. Ancajas (MS EE 2010), “Resource Allocation in X86 Simultaneous Multithreading (SMT) Processors“
  • Jestoni V. Zarsuela (MS EE 2010), “A Study of Cache Sub-Banking and Block Buffering as Power Reduction Techniques for Multiprocessor Cache Design“
  • Tanya Vanessa F. Abaya (MS EE 2010), “Frequency Synthesizers in 90nm CMOS for WiMax Receivers“
  • Sherwin Paul R. Almazan (MS EE 2010), “A 10MHz 3rd Order Butterworth Gm-C Low-Pass Filter in a 90nm CMOS Process“
  • Lendl Israel M. Alunan (MS EE 2010), “System-Level Analog Architectural Design for WIMAX Direct-Conversion Receivers in 90nm CMOS“
  • Michael Angelo G. Lorenzo (MS EE 2010), “Comparison of Integrated LNA-Mixer Topologies for WIMAX Application in a Standard 90nm CMOS Process“

2009

  • Wilson M. Tan (MS EE 2009), “Asymmetric Clustering of Microarchitectures Through Dynamic-Selective Shutdown and Sharing of Functional Units“
  • Gian Paolo T. Mayuga (MS EE 2009), “A Study of the Design Methodologies of RF CMOS Mixers for Low-IF Receivers“

2008

  • Jennifer M. Jayme (MS EE 2008), “Analysis of Different Amba-Based Bus Interconnection Schemes for ARM7 Multi Core Environment“

2007

  • Edmund Cornelius V. Manlangit (MS EE 2007), “A Study on the Design of Fully-Integrated RF CMOS Low-Noise Amplifiers for 2.4 GHz Application“
  • Lilibeth Anne P. Gahol (MS EE 2007), “A Study of Selective Power-Down Techniques for the ARM7 Microprocessor“
  • Edward Bryann C. Fernandez (MS EE 2007), “A Study of Snoopy Cache Coherence Protocols for Dual Processor Systems“

2005

  • Christian Raymund K. Roque (MS EE 2005), “A Study of the Effects of Noise Matching on the Design of RF CMOS Low Noise Amplifiers“
  • Joy Alinda P. Reyes (MS EE 2005), “A Study of Floating-Point Architectures for Pipelined RISC Processors“

2004

  • Honee Lynn B. Tan (MS EE 2004), “Characterization, Comparison and Analysis of Monolithic Capacitors in Silicon for RFICs“
  • Alberto B. Realo, Jr.  (MS EE 2004), “A Study of Different Encoding Techniques Applied on Hihg-Capacitance Buses for Low-Power Processor Design“
  • Jeffrey M. Mendiola (MS EE 2004), “Analysis of Clock Manipulation Schemes for Low Power Design“
  • Richard B. Borja (MS EE 2004), “A Study of the Effects of Pipeline Modification Techniques on the Performance and Power Consumption of the DLX“
  • Sihawi A. Khalid (MS EE 2004), “A Study of Selective Power-Down Techniques for Low-Power RISC Microprocessor Design“
  • Maria Theresa A. Gusad (MS EE 2004), “A Study of the Effects of Power Matching Techniques on the Performance of RF CMOS  Low-Noise Amplifiers“
  • Anastacia P. Ballesil (MS EE 2004), “A Study of Translation Lookaside Buffer Structures for Low Power Consumption“

 2003

  • Crimson S. Pornela (MS EE 2003), “A Study of the Effects of Layout Techniques on the Noise Performance of CMOS RF Transistors“
  • Arianne C. Bantug (MS EE 2003), “A Study of Selective Power-Down Optimization Techniques for Low-Power Integrated RISC Execution Unit Design“
  • Maria Cecilia N. Gutierrez (MS EE 2003), “A Study of the Effects of Layout on RF MOSFET Small-Signal Parameters“
  • Archie C. Te (MS EE 2003), “A Study on Using Dual Supply Voltages for Low Power Design of Data Path Elements for a RISC Microprocessor“
  • John Richard E. Hizon (MS EE 2003), “A Study of Planar Inductor Coupling on a 0.25um Epitaxial CMOS Process“
  • Marc D. Rosales (MS EE 2003), “Characterization, Comparison and Analysis of Monolithic Inductors in Silicon for RFIC’s“
  • Joel R. Noche (MS EE 2003), “An Asynchronous Single-Precision Floating-Point Arithmetic Unit“