Class Information

• Course Information
  • Title: Advanced Digital Design
  • Description: Combinational and sequential circuits. Structured design. Digital design using programmable devices. HDL-based digital design. Simulation. Testing of digital circuits.
  • Credit: 3 units (2-hour lecture, 3-hour laboratory)
  • Corequisite: EEE 105 (Computer Organization)
• Schedule
  • Lecture
    • TLM: T 4PM-6PM, EEEI LC1
  • Laboratory
    • TLMWXY: W 2:30PM-5:30PM, EEEI 428
    • TLMFXY: F 2:30PM-5:30PM, EEEI 428
• Instructors
  • Fredrick Angelo R. Galapon (fredrick.galapon@eee.upd.edu.ph)
  • Anastacia B. Alvarez (anastacia.alvarez@eee.upd.edu.ph)

Announcements

• 08/12: Welcome to CoE 111!
• 08/19: ME 1 has been re-uploaded to reflect necessary corrections for the FPGA implementation.
• 08/20: Today is the UP Day of Walkout and Action. With that, we will not check attendance on the lecture class later to accommodate those who would like to join the protest.
• 08/23: For the Wednesday class, Room 428 will be open for FPGA testing on Aug. 27 (Tuesday), 1PM-4PM.
• 09/16: If you have any conflict with the schedule of LE 1 and would like to request for early exam (8AM-10AM) or late exam (10AM-12PM), please fill out this form by tomorrow, Sep. 17 (Tuesday).
• 09/17: Submit your problem sets tomorrow at Room 220 by 2PM. Answer key for the problem set will be released tomorrow. Also submit at least four A4 sheets (for your exam on Saturday). Write your name and student number on the upper right corner of each paper. 
• 09/18: The regular schedule for LE 1 is 9AM-11AM. The room assignments are Room 123 and Room 229 for the Wednesday and Friday laboratory classes, respectively. As for the early exam, the schedule is changed to 7AM-9AM. Please wait for further announcement regarding the room. Only the following students are expected to take the early exam:
  • Accad
  • Adamos
  • Cruz
  • Henson
  • Lim
  • Macasaet
  • Pante
  • Salgado
  • Saulo
• 09/19: The room assignment for the early exam is Room 320.
• 10/08: The grading sheet can be found here. If there are inquiries, concerns, or inconsistencies in the grading sheet, kindly email me.
• 10/14: For early exam 2 (7AM-9AM) request, please fill out this form by Oct. 22 (Tuesday).
• 10/25: Only the following students are expected to take the early exam (LE 2):
  • Abanto
  • Accad
  • Cruz
  • Henson
  • Lim
  • Pante
  • Salgado
  • Saulo
• 11/12: We will not meet for lecture class today. The deadline of the homework is moved to Nov. 19 (Tuesday), 4PM.
• 12/02:
  • We’ll have your last exam (LE 3) on Dec. 9 (Monday), 1PM-4PM, VLC. Only Lectures 7 and 8 will be included in the exam. Answer sheets will also be provided.
  • Submit your HWs by Dec. 6 (Friday) at Room 220.
  • There will be an open lab on Dec. 4 (Wednesday) and Dec. 6 (Friday), 1PM-5PM.
  • Checking of MPs will be done on Dec. 11 (Wednesday) and Dec. 13 (Friday), 1PM-5PM, for the Wednesday and Friday classes, respectively. Deadline of documentation and source code submission is on the day of your MP checking.
• 12/04: Due to the suspension of classes, there will be no open lab today. Stay safe, everyone!
• 12/04: There will be an open lab on the following days: Dec. 5-6 and Dec. 10-12, 1PM-5PM. We’ll also move the deadline of the MP to Dec. 13 (9AM-12PM for the Wednesday class, and 1PM-4PM for the Friday class). Good luck!
• 12/12: The deadline of the MP is moved to Dec. 17 (9AM-12PM for the Wednesday class, and 1PM-4PM for the Friday class). If you have any conflict with the schedule, kindly email me. The lab will be open on Dec. 13 and Dec. 16, (9AM-4PM), for FPGA testing. Also note that the minimum specifications for the MP is LCD initialization. 

Exams

• LE 1: Sep. 14 (Saturday), 9AM-11AM Sep. 21 (Saturday), 9AM-11AM
• LE 2: Oct. 19 (Saturday), 9AM-11AM Oct. 26 (Saturday), 9AM-11AM
• LE 3: Nov. 23 (Saturday), 9AM-11AM Dec. 9 (Monday), 1PM-4PM

Homework

• HW 1: Due on Nov. 12 (Tuesday), 4PM Nov. 19 (Tuesday), 4PM. (solution)
• HW 2: Due on Nov. 26 (Tuesday), 4PM. (solution)

Problem Set

• PS 1: Due on Sep. 17 (Tuesday), 4PM Sep. 18 (Wednesday), 2PM. (solution)
• PS 2: Due on Oct. 22 (Tuesday), 4PM.

Lecture Materials

Lecture	Title	Slides
	Syllabus	pdf
00	Introduction	pdf
01	Hardware Description Language	pdf
02	Behavioral Modeling	pdf
03	Sequential Circuits	pdf
04	Interfacing and Some Common Building Blocks	pdf
05	Register-Transfer Level	pdf
06	Programmable Devices & Issues in Digital Design	pdf
07	State Identification	pdf
08	Fault Modeling	pdf
09	DFT and BIST	pdf

Laboratory Materials

• References for the Artix-7 35T FPGA Arty Evaluation Kit
  • Reference Manual
  • Board File – Place this folder in data/boards/board_files inside the Vivado installation directory.
  • Xilinx Design Constraint (XDC) file
• ME 1: Familiarization with Xilinx Vivado Design Suite
  • Source Files
• ME 2: Structural Modeling
  • Source Files
• ME 3: Behavioral Modeling of Combinational Circuits
  • Submission Link
  • Automated Checker Testbench
• ME 4: Finite-State Machine
• ME 5: Register-Transfer Level (RTL) Design
  • Sequential Multiplication and Division (lecture slide from EEE 105)
  • Automated Checker Testbench
  • Automated Checker Testbench (for late checking)
• ME 6: RGB LED
• MP: LCD and RGB LED Interface
  • Schematic
  • LCD User Manual
  • Submission Link

References

• Thomas and Moorby, “The Verilog Hardware Description Language”. 5th ed. 2002. Springer.
• Mano and Ciletti, “Digital Design”. 5th ed. 2012. Pearson.
• Smith, “Application-Specific Integrated Circuits”. 1997. Addison-Wesley Professional.
• Weste and Eshraghian, “Principles of CMOS VLSI Design: A Systems Perspective”. 1985. Addison-Wesley.
• Bushnell and Agrawal, “Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits”. 2004. Springer.
• Weste and Harris. “CMOS VLSI Design: A Circuits and Systems Perspective”. 4th ed. 2010. Pearson.