CoE 111: Advanced Digital Design (1st sem AY 2016-2017)

Class Information

  • Lecture Schedule: Fridays 10:00am – 12:00pm, EEEI LC1
  • Laboratory Schedules
  • Exam Schedule
    • First Exam: 17 Sept 2016, VLC 11am-1pm
    • Second Exam: 22 Oct 2016, VLC 11am-1pm
    • Third Exam: 3 Dec 2016, VLC 11am-1pm

Announcements

  • 1/3: Removal exam will be on Saturday, Jan 7 at 1PM. E-mail me for any conflicts -Snap
  • 12/19: Tentative lecture grades are already posted here. Students with lecture grades between 28 to 30 will be given a 4.0 and will have to take a removal exam (TBA). As I am out of the country, any rechecking of exams will have to be done through e-mail. Just scan or take a picture of the part to be rechecked and provide a justification for a higher mark. Exam 3 papers may also be claimed outside room 409. -Snap
  • 12/15: Exam 2 results already posted. Exam papers may be claimed outside room 409.
  • 12/9: MP submission has been extended. Checking after the original deadline (which has already passed) will merit half of the incremental points. For example, you already have 20 points from being able to write to the LCD. If you are able to achieve buffered driver operation on the extension, you will get 20 + (50/2) + docu grade. Documentation will still be submitted on Dec 10, so only your progress for the original deadline will need to be documented (and subsequently graded). Final checking will be done on Tuesday, 1-5PM. For testing, the lab will be opened on Monday, from 9AM to 5PM. Code for your final work will still have to be submitted, otherwise the incremental points will not be recorded. Documentation for any incremental work WILL NO LONGER BE REQUIRED.
  • 12/5: Class standings may be viewed here. Exam 1 results are already posted.
  • 11/29: STC will be open (for FPGA testing purposes) on Tuesday-Friday 11:30AM-2:30PM this week and on Monday next week (5 Dec) 1PM-5PM.
  • 11/24: Lecture class review tomorrow. Attendance will not be checked. Deadline for submission of answer sheets will be on Tuesday, 29 November 2016.
  • 11/2: No Lab class today (for the WED CLASS ONLY)
  • 10/10: No Lab Classes this week (Oct.10-14).
  • 9/13: Exam 1 will push through on Saturday (17 Sept). Coverage will be lectures 1 to 3.
  • 8/16: Welcome to CoE 111!

Lecture Slides

Lab Resources

EDA tools environment variables

Create a BASH script file (ex. setup_synopsys.sh) with the following contents. Whenever you need to run the EDA tools, just run this script before running the tools (ex. source setup_synopsys.sh).

#!/bin/bash
## License
export LM_LICENSE_FILE=27000@10.158.16.12
## VCS
export VCS_HOME=/eeei/tools/synopsys/vcs-mx/H-2013.06-SP1/
export VCS_BIN=/eeei/tools/synopsys/vcs-mx/H-2013.06-SP1/bin
## SYN
export SYN_BIN=/eeei/tools/synopsys/syn/I-2013.12/bin
## PATH
export PATH=$VCS_BIN:$SYN_BIN:$PATH

Lab Exercises