Microlab Undergraduate (198/199) Projects

AY 2023-2024

Second Semester

  • A Low-Noise, Low-Power Nested Chopper Amplifier in 22nm CMOS FD-SOI Process for a Thermopile-Based Temperature Sensor
    • Jose Adolfo Talactac
    • Advisers: MTGD, JREH, MDR, RMP, AGL, MSCR, VABGR
  • Low Power SAR-ADC using Non-Uniform Sampling for ECG application
    • Soc Tuason
    • Advisers: MTGD, JREH, MDR, RMP, AGL, MSCR
  • Analytical Modelling, Miniaturization, and Optimization of Diaphragm Structures for Piezoresistive Intracranial Pressure Monitoring
    • Mary Trixia Elyonne Baynosa, Recca Maica Cañeja, Matthew Leaño, Justin Brian Quijana
    • Advisers: MTGD, RMP, RMMG
  • A Comparative Study on Different Interdigitated Transducer Configurations in MEMS-based SAW Temperature Sensors for High Temperature Applications
    • Ian Benedict De Guzman, Juan Paolo Isaac, Clarence Nico Concepcion, Vittorio Mercurio
    • Advisers: MTGD, RMP, RMMG
  • Development of a Low-Power LNIA-ADC Interface of a Thermopile Sensor for Biomedical Application
    • Jeremy David Molines, Zylm Sabater, Fergie John Frange, Eugene Imbang
    • Advisers: MTGD, JREH, MDR, RMP, AGL, MSCR, VABGR
  • Implementation of an Energy-Quality Scalable AI Accelerator Engine for TinyML Applications
    • Kenn Danielle Pelayo
    • Advisers: ABA, ANC, FAG, LRQ, AJT
  • Peripheral Block Extension of a Reconfigurable 8T SRAM In-Memory Computing Macro for High-Throughput MAC Operations
    • Brian Angelo Camba, Aliyah Marie Collada, Kenrick Wu
    • Advisers: ABA, ANC, FAG, LRQ, AJT
  • Memristors for Associative Memory in Hyperdimensional Computing
    • Terence Daniel Manansala, Benjamin James Pineda
    • Advisers: ABA, ANC, FAG, LRQ, AJT, RT
  • Design of a Charge Pump Circuit in a Thermoelectric Energy Harvesting System for Wearable Device Applications
    • Celianne Jadd Atienza
    • Advisers: MTGD, JREH, MDR, ZRAS, AGL, MSCR
  • A 6.5 – 8.0GHz Process Variation-Aware Low-Power IR-UWB Transmitter Front-End in 22nm FD-SOI
    • Mark Lester Cuaresma, Emmanuel Jesus Estallo, Han Espinosa, Andre Mikhail Serra
    • Advisers: LPA

AY 2022-2023

Second Semester

  • Low Power, High Bandwidth FD-NIRS Optical Receiver Front-End Circuits in 28nm FD-SOI for muscle Oxygenation Monitoring Systems
    • Dianne Jade Cristobal, Elyssa Nicole Pablo, Rodmar Ramos, Jessica Marie Rondaris, Andrea Zefaniah Timpug
    • Advisers: MTGD, JREH, MDR
  • Redundancy Pruning for Associative Memories in Sparse Hyperdimensional Computing for Energy-efficient Speech Recognition
    • Kim Isaac Buelagala, Ginzy Javier, Sean Alfred Lipardo, James Carlo Sorsona
    • Advisers: ABA, RAA, SJAB, FAG, LRQ, AJT
  • 10 Gb/s Energy-efficient Optical Transceiver using 1060 nm HCG MEMS-tunable VCSEL in 28nm FD-SOI
    • Christian Cortes, Jan Paolo Cortez, Juhaina Angela Custodia, Kevin Mathew Reyes, Mariane Sta. Barbara
    • Advisers: MTGD, JREH, MDR
  • Investigation on the Effectiveness of using Body Biasing Techniques in the Design of Voltage-Scaled and PVT-Invariant Miller OTAs for Biomedical Applications in 28nm FD-SOI Technology
    • Aylwin Orlando Almario, Jiro Camua, Julian Doblon, Angela Marie Hinlo, Emmanuel Paulo Santos
    • Advisers: MTGD, JREH, MDR, JMMM, ZRAS, AGL, MSCR
  • Low Noise and Low Power Analog Front-End Unit for Wearable EEG Systems
    • Zayyir Ulric Cornelio, Paolo Resurreccion
    • Advisers: MTGD, JREH, MDR
  • Hardware-optimized Machine Learning Model Comparison for Human Activity Recognition using MEMS Tri-axial Accelerometers
    • Kei Palabasan, Ramona Rajagopalan
    • Advisers: MTGD, JREH, MDR, JMMM
  • A Comparative Study of Capacitively-coupled (CCIA) and Curren-Feedback Instrumentation Amplifiers (CFIA) for Signal Conditioning of MEMS Piezoresistive Pressure Sensors
    • Kyla Marie Juruena, Trixi Emmanuelle Obar, Adam Jefferson Ramones, John Robert Siglos, Paolo Miguel Villacorta
    • Advisers: MTGD, JREH, MDR, JMMM, ZRAS, AGL, MSCR
  • Carrd: A Reconfigurable RISC-V Vector Coprocessor for Artificial Neural Networks
    • Raine Kayla Alegre, Celine Joy Capua, Alexandria Marie Lopez, Dimple Mae Manalo
    • Advisers: ABA, RAA, SJAB, FAG, LRQ, AJT
  • Integration of In-Memory Computing Capabilities to a Self-Matching Complementary-Reference Sensing Scheme for Toggle Spin Torque Magnetic Random Access Memory
    • Christopher Camarillo Jr., Giussepe Yvanric Galvez, Andrew James Lim, John Rey Marturillas, Mark Emmanuel Teodoro, Ellris Kristian Neil Urfano
    • Advisers: ABA, RAA, SJAB, FAG, LRQ, AJT
  • Modeling and Simulation of MEMS Piezoelectric Pressure Sensor with Variation of Microstructures for Voltage Sensitivity Optimization
    • Joshua Glenn Cagas, Chester Paglinawan, Rexter Xavier Matthew Saquilayan, Carl Andrei Sto Domingo, Mikel Antonella Valeriano
    • Advisers: MTGD, JMMM, RMP
  • 10-bit Low Power SAR ADC with 2-Stage Dynamic Latched Comparator and Split-Monotonic Capacitive DAC for MEMS Sensor Readout
    • Ron Brian Bodomo, Alyssa Leila Bugas, Francine Alyana Juan, Ivan Jacob Juan
    • Advisers: MTGD, JREH, MDR, JMMM
  • Co-design of MEMS-based Thermoelectric Temperature Sensor and Interface Circuit
    • Ralph Maru Grande, Vincent Angelo Bogg’s Roxas
    • Advisers: MTGD, JMMM, RMP
  • Modeling and Characterization of MEMS-based Four-Ended Beam Thermopile Thermoelectric Temperature Sensor
    • Leila Marie Gaffud
    • Advisers: MTGD, JMMM, RMP

AY 2021-2022

Second Semester

  • A 5-stage Pipelined RISC-V Processor with Vector Expansion Support for CNN Operations
    • Jerome Cedrick Magtibay
    • Advisers: RAGA, ABA
  • Low Noise Instrumentation Amplifier for MEMS Sensor Interface and Signal Conditioning
    • Neil Angelo Aballa, Benedict Nathan Sarino
    • Advisers: LPA, MTGD, JREH, MDR
  • CMOS-based Piezoelectric Energy Harvesting Circuit for Wearable Applications using PVDF Films
    • Charles Louis Dela Rosa, Crispin Michael Babaan, Christian Kenneth Basaysay, John Vincent Santos
    • Advisers: LPA, MTGD, JREH, MDR
  • An IR-UWB IEEE 802.15.4a Transmitter System Modelling
    • Trisha Renee Capulong, Danielle Karla Quijano, Maria Ena Rosales
    • Adviser: LPA
  • Magnetoelectric Spin-Orbit Based Digital Circuits
    • Dan Dave Acosta, Joseph William Doctor
    • Advisers: RAGA, ABA
  • Energy-Efficient Speech Recognition Using Sparse Hyperdimensional Computing
    • James Andrei Caguicla, Reynaldo Jaime Gonzalez, Fransandreimannuel Colendres
    • Advisers: RAGA, ABA
  • STT-MRAM-based Bulk-Bitwise In-Memory Computing Architecture for Binary Convolutional Neural Network Acceleration
    • Gian Ezekiel Calpo, Gryan Carl Galario, Ivan Gabriel Etorma
    • Advisers: RAGA, ABA

AY 2020-2021

Second Semester

  • Modeling Pseudo-differential Ring Oscillator in Verilog-A for Power Minimization
    • Roger Brian Santos
    • Advisers: ABA, MTGD, JREH, MDR, MPRS, CGS
  • A Voltage Controlled Magnetic Anisotropy (VCMA) Magnetic Tunnel Junction (MTJ)-based Random Number Generator (RNG) Module
    • Lawrence Roman Quizon
    • Advisers: MPRS
  • RISC-V Design Using Verilog
    • Margarette Lipayon
    • Advisers: ABA

AY 2019-2020

Second Semester

  • Design and Implementation of a Pipelined RV32IMC Processor with Interrupt Support for Large-Scale Wireless Sensor Networks
    • Victor Emmanuel Baylosis, Phoebe Meira Chua, Michael Joseph Neri, Redentor Immanuel Ridao, Allen Jason Tan
    • Advisers: ABA, MTGD, JREH, MDR, MPRS, CGS
  • Character Recognition using Sparse Hyperdimensional Computing on 65nm CMOS Standard Cell
    • Jane Rainiel Delos Santos
    • Advisers: ABA, MTGD, JREH, MDR, MPRS, CGS
  • A Write Latency Optimized Spin-Orbit Torque Magnetic Random Access Memory with Spin-Transfer Torque Assist for Cache Application
    • Adrian Caburnay, Jonathan Gabriel Reyes
    • Advisers: ABA, MTGD, JREH, MDR, MPRS, CGS
  • An OOK RF Transceiver System Model in Verilog-A for System Performance and Power Optimization
    • Arriel Ting, Daniel Angelo Tobias
    • Advisers: ABA, MTGD, JREH, MDR, MPRS, CGS
  • Design and Implementation of a Piezoelectric Energy Harvester Interface Circuit using Synchronous Electric Charge Extraction for Shock Inputs
    • Christian Joseph Dia, Ralfael Himor
    • Advisers: ABA, MTGD, JREH, MDR, MPRS, CGS
  • Implementation of a USB 2.0 Type-C Controller Interface for RISC V Processor in FPGA
    • John Erasmus Mari Geronimo, Carl Vincent Valencia, Kierc Velasco
    • Advisers: ABA, MTGD, JREH, MDR, MPRS, CGS
  • Verilog-A Modeling of a 2.4-GHz Zigbee Receiver Front End
    • Renzo Nicolas Alsim
    • Advisers: ABA, MTGD, JREH, MDR, MPRS, CGS
  • FPGA-based Features Extraction Sensor for Lettuce Crop
    • Maverick Jonas Adonis, Renzo Forteza, Alaine Richelle Ramos
    • Advisers: ABA, MTGD, JREH, MDR, MPRS, CGS
  • 5Gb/s Optical Transceiver for MEMS Tunable HCG-VCSEL in 65nm CMOS
    • Francesca Bea Narcida, Sean Kane Lloyd Quintans, Janelle Eira Tordesillas
    • Advisers: ABA, MTGD, JREH, MDR, MPRS, CGS

AY 2018-2019

Second Semester

  • A VCSEL-Based Optical Transceiver operating up to 1 Gb/s in 65nm CMOS with Compensation for Signal Distortion
    • Omar Renz Regalado, Eurielle Santos, Jerome Vincent Tagaro
    • Advisers: ABA, MTGD, JREH, MDR, CGS
  • Implementation of a Physical Layer WSN Testbed using SDR
    • Herlan Kester Benitez, Haven Christian Cabuso
    • Advisers: ABA, MTGD, JREH, MDR, CGS
  • Design and Implementation of a Self-starting Thermal Energy Harvester with Resonant Startup and Maximum Power Point Tracking Capabilities for Wireless Sensor Nodes
    • Joenard Matanguihan, Phoebe Laine Panis, Maria Sophia Ralota
    • Advisers: ABA, MTGD, JREH, MDR, CGS
  • Implementing a Single-Cycle RISC-V 32-bit Baseline Processor with Compressed Instruction Extension for the Wireless Sensor Nodes of RESE2NSE
    • Bruce Arenas, Sean Michael Calingasan, Elbien Itaas, Reymart Lingad, Philip Jhurell Pati, Edgardo Ragasa Jr.
    • Advisers: ABA, MTGD, JREH, MDR, CGS
  • Implementation of a USB 2.0 Type-C Port Device Controller for Sensor Network Integration on a 65 nm CMOS Process
    • Lucas Niegel Cabading, Allen Cedrick Domingo, Johnel Isaac Manalili, Ronnel Tehrence Paclibar, Eyanne Kyle Ranjo, Aiken Earl So
    • Advisers: ABA, MTGD, JREH, MDR, CGS
  • Design and Implementation of a Baseband LoRa Demodulator using De-chirp Method
    • Dan David Estarija, Katreena Gabrielle Juntado, Miguel Lorenzo Panagsagan
    • Advisers: ABA, MTGD, JREH, MDR, CGS
  • Varying Resolution Pipelined ADC for Direct IF Sampling Receiver in Wireless Sensor Networks
    • Jasper Jamir, Jeffrey Louise Reyes, John Carlo Roberto
    • Advisers: ABA, MTGD, JREH, MDR, CGS
  • Hardware-based Model of Energy-Efficient Routing and MAC Protocols Using Machine Learning
    • Lester Bacay Jr., James Andrew Formales
    • Advisers: ABA, MTGD, JREH, MDR, CGS
  • Using Hyperdimensional Computing for Character Recognition on 65nm CMOS Standard Cell
    • Alec Xavier Manabat, Celine Rose Marcelo, Alfonso Louis Quinquito
    • Advisers: ABA, MTGD, JREH, MDR, CGS
  • An Automated Design of CMOS Operational Amplifiers Using gm/id Methodology with Compensation for Process and Temperature Variations in 65nm Technology
    • Ezra Deb Batausa, Stephen James Ninte
    • Advisers: ABA, MTGD, JREH, MDR, CGS
  • Design and Implementation of Piezoelectric Energy Harvester Interface Circuit using Synchronous Electric Charge Extraction with Self-Startup Capability for Wireless Sensor Nodes
    • Jeremy Karl Diaz de Rivera
    • Advisers: ABA, MTGD, JREH, MDR, CGS

AY 2017-2018

First Semester

  • A 2.4GHz Energy-efficient Short-range Receiver with Variable Gain and Wake-up for Wireless Sensor Networks
    • George Procyon Cabrera, Jhelsea Credo, Gio Ishmael Evidente, Ralen Rose Gloria Malatbalat, Steven Lorenz Mindoro, Arlo Ricardo Sanico
    • Advisers: ABA, CVJD, MTGD, RJMM, MDR

Second Semester

  • Low Power Converter for Capacitive Sensors using Capacitance-to-Pulse Width Modulation
    • Arexius Vico Balde, John Owen Cabuyadao
    • Advisers: CVJD, MTGD, JREH, RJMM, MDR
  • A Study on Coarse Stage Bit Allocation to Improve Power Efficiency of a 10-bit Coarse-Fine SAR ADC Implemented in 65nm CMOS Process for Environmental Sensing Applications
    • Uziel Rein Agub, Jhake Zebedee Aquino, Justine Beano, Rommel Monsayac
    • Advisers: ABA, CVJD, MTGD, JREH, RJMM, MDR
  • A Low-Power All-Digital Phase-Locked Loop for a DVFS System on a Processor for Wireless Sensing Applications
    • Mark Allen Agaton, Fredrick Angelo Galapon, Arcel Leynes, Lemuel Neil Noveno
    • Advisers: ABA, CVJD, MTGD, JREH, RJMM, MDR
  • A gm/ID Based Algorithm for the Design of CMOS Miller Operational Amplifiers in 65nm Technology
    • Zyrel Renzo Sanchez, Sam Jason Vasquez
    • Advisers: MTGD, JREH, RJMM, MDR
  • Design and Implementation of a Thermoelectric Energy Harvesting Interface Circuit with Maximum Power Point Tracking and Self-Startup Capability for Wireless Sensor Nodes
    • Abigail Antenor, Kristine Campang, Khristen Anne Rafols
    • Advisers: ABA, CVJD, MTGD, RJMM, MDR
  • Implementation of an H.264 Baseline Profile Encoder with Variable Prediction Complexity using Partial Reconfiguration
    • Noelle Beatrix Cabigao, Maria Carmina Rae Gonzaga, Hazel Laure
    • Advisers: ABA, CVJD, MTGD, JREH, MDR
  • Hardware-Based Model of Node Clustering using Machine Learning for Wireless Sensor Networks
    • Gienel Francheska Manarang, Rusty John Lloyd Mina, Mikko Chino Salvador
    • Advisers: ABA, CVJD, MTGD, MDR
  • A Study on the Effectiveness of using a Hybrid Topology in Improving the Power Efficiency and Voltage Regulation over a Wide Input Range of DC-DC Converters
    • Kenny Yu
    • Advisers: MTGD, RJMM

AY 2016-2017

First Semester

  • ENOB Degradation of an 8-bit 1 Msps SAR ADC in 65nm CMOS under Supply Voltage Scaling
    • Brian Carlo Basco
    • Advisers: LPA, CVJD, MTGD, MDR

Second Semester

  • Designing Wireless Transceiver Blocks for LoRa Application
    • Matthew De Vera, Cathlene Mae Garcia, Levi Klein Marifosque, Jessica Palafox, Denise Soriano
    • Advisers: LPA, CVJD, MTGD, RJMM, MDR
  • Design of Sigma-Delta Analog-to-Digital Converters Implemented in 65nm Digital CMOS Process for LoRa
    • Doreen Dellosa, Mel-Jie Bentz Del Mundo, Gelyn Manzanares, Edrian Daniel Marqueses, Edzhel Rose Valverde
    • Advisers: LPA, CVJD, MTGD, RJMM, MDR
  • A Study on Partial Reconfiguration with Compression via Modularizing Secondary Processes of a General Purpose Processor
    • Eimabelle Clavo de Comer, Vance Anthony Coronel, Yves Lean Krishner Macayana, Lorenzo Martin Manalac, Alexis Czezar Torreno
    • Advisers: LPA, CVJD, MTGD, RJMM, MDR
  • A Study on the Effects of Dynamic Voltage and Frequency Scaling on an Error Detection System for a LoRa Communications System
    • Jahn Caroll Dimayuga, Ian Christian Fernandez, Alfonso Elias Lopez, Rafael Pangilinan
    • Advisers: LPA, CVJD, MTGD, RJMM, MDR
  • Designing a Maximum Power Point Tracking System and an LDO Regulator for Interface Circuits of Solar Energy Harvesters for LoRa Sensor Nodes
    • Marc Anthony Huab
    • Advisers: LPA, CVJD, MTGD, RJMM, MDR

AY 2015-2016

First Semester

  • Error Rate Control Through Dynamic Frequency Scaling for Minimum-Energy Point Operation in Razor-Based Processors
    • Eugene John Lim

Second Semester

  • Implementation of Programmable Dynamic Voltage and Frequency Scaling on a Processor for Wireless Sensing Applications
    • Ryan Albert Antonio, Rafael Mari de la Costa, Aldrin Rolf Ison, Wesley Kaiser Lim, Robert Adrian Pajado, Deanne Bianca Roque, Ruelle Martin Yutuc
    • Advisers: LPA, CVJD, MTGD, MDR
  • Digital Low Dropout Voltage Regulator with Feedback
    • Dexter Darwin Bernardo, Justine Luis Lopez, Marc Derik Lopez
    • Advisers: LPA, CVJD, MTGD, MDR
  • Switched Capacitor Regulator with Feedback
    • John Jairus Eslit, Kate Kristian Olasiman, Antonio Karlos Uy
    • Advisers: LPA, CVJD, MTGD, MDR

AY 2014-2015

Second Semester

  • Reduction of Process Variation Effects on an Amplifier of a 10-bit pipelined ADC and a LDO Regulator Using Digital Circuit Assistance Techniques
    • Bianca Bote, Michael de los Reyes, Maria Lourdes Docdoc
  • Digitally Assisted Analog Amplifiers to Compensate for Supply Voltage Variations
    • Bryan Edward Ayson, Aldon Cris Galido
  • Reduction of Temperature Effects in a Pipelined ADC Residue Amplifier and an LDO
    Error Amplifier Via Digital Assistance
    • Joaquin Carlos Almirante, Jose Maria Guevara, Joel Savier Ng
  • Amplifier Nonlinearity Compensation Using Digitally Assisted Architectures
    • Leo Alfonso Abella, Neil Christian Astrologo, Miro Jan Benedict Navarro
  • Minimizing the Effects of Process Mismatch in 10-b SAR ADC Using Digital Assistance
    • Arvin Wilson Alba, Katrina Claire Hernandez, Reyben Patrick Liwag