CoE 23: Synthesis of Sequential Circuits (1st sem AY 2014-15)

Class Information

  • Instructor:
  • Lecture: THV TTh 11:30-12:30pm EEEI 120
  • Lab:
    • THVM: Monday 1-4pm EEEI STC (308)
    • THVW: Wednesday 7-10am EEEI STC (308)
    • THVF: Friday 2:30-5:30pm EEEI STC (308)
    • THVS: Saturday 1-4pm EEEI STC (308)

Announcements

  • No lab classes on the week of August 10.
  • August 19 and 21 were declared as holidays. No lecture classes on those dates. Lab classes will meet.
  • August 25-30: No lab exercises to be released this week. Finish implementing lab 1 in HADES. Monday lab class: You can email your work to me (in .hds format), with the subject CoE 23 THVM Lab 1 ‘Surname’.
  • Please do Quiz 1 in HADES as practice.
  • September 2: Do the practice problem in Lecture 2.5.
  • September 16: Release of Design Problem 1 Specifications
  • October 7-11: Checking week of DP1
  • October 23: Quiz 7: Create an asynchronous machine that transitions into the next LED ‘state’ whenever a pulse (positive edge) is received from the input X. The system has three output LEDs (name it Y2, Y1, and Y0) that light up in the following order: 001, 100, 110, 101. The pattern then repeats whenever the last pattern is reached.

    Go through all the steps of asynchronous circuit synthesis as indicated in the lecture, except for the last one (no need to draw the circuit). Provide all the necessary explanations while going through each step. 2 points for each step (for a total of 10 points) will be given to those with complete ‘bobo-friendly’ explanations.

  • For the Lab Exercise 5, you will be implementing Quiz 7 in HADES. Moreover, try to think of a synchronous sequential circuit equivalent of the system and implement that side by side with the original. The input should be the same and the output LEDs for each system should behave similarly.

    Note: You might encounter a problem wherein the circuit becomes unstable (switches back and forth from 0 to 1) even though in theory it should not. This is because HADES strictly follows the numerical propagation delays present in the circuit. In real life, however, this should not happen. This simulation issue can be solved by applying a zero propagation delay to all the logic gates involved in the state transition except for the feedback path (the AND gate that initializes the whole circuit).

  • October 30: Submission of Quiz 7 during the Lecture session
  • November 3,5: Monday and Wednesday lab classes will meet for Lab 5 checking
  • November 7: Friday lab class will meet for Lab 4 work and Lab 5 checking
  • November 8: Saturday lab class will meet for Lab 5 checking and Lab 6 work

 

Lecture Slides

Lab Exercises