- Analog Integrated Circuits
- Lectures: Tuesdays and Thursdays, 10:00am – 11:30am, Rm. 307 (EEEI)
Announcements
- 6/6: Welcome to EE 220!
- 7/2: Assignment #1 is here. Due Tuesday, 7/19.
- The 90nm PTM model file is here.
- 7/11: No class today.
- 8/17: Assignment #2 is here. Due Tuesday 8/27.
- 8/19: No class on 8/20. Just attend the ADI talk at the UPAE Centennial Hall, Accenture Rm, from 9am-12nn.
- 8/29: Since not all students can make today’s class, there will be no class today.
- 9/16: Since not all students can make it to tomorrow’s class, there will be no class on 9/17.
- 10/1: Project specifications are here. Due Monday 10/21.
Class Lectures
| Date | Title | Slides | |
|---|---|---|---|
| 1 | 6/6 | Introduction | |
| 2 | 6/11 | CMOS Technology and Passive Devices | |
| 3 | 6/13 | CMOS Technology and Passive Devices | |
| 6/18 | No Class (UP Foundation Day) | ||
| 4 | 6/20 | MOS Transistor Modeling | |
| 6/25 | No Class | ||
| 6/27 | No Class | ||
| 5 | 7/2 | Design Driven Small Signal Models | |
| 6 | 7/4 | Design Driven Small Signal Models | |
| 7 | 7/9 | Electronic Noise | |
| 8 | 7/11 | Noise Analysis | |
| 9 | 7/16 | Review of Feedback | |
| 10 | 7/18 | Feedback Analysis | |
| 11 | 7/23 | Noise and Feedback | |
| 12 | 7/25 | Current Sources | |
| 13 | 7/30 | Amplifiers | |
| 14 | 8/1 | Single-Ended and Differential OTAs | |
| 15 | 8/6 | Folded-Cascode OTAs | |
| 16 | 8/8 | Feedback and Stability | |
| 17 | 8/13 | Settling | |
| 18 | 8/15 | Settling | |
| 19 | 8/20 | A Design Example | |
| 20 | 8/22 | Common-Mode Feedback | |
| 21 | 8/27 | Multi-Stage Amplifiers | |
| 22 | 8/29 | Biasing and References | |
| 23 | 9/3 | ||
| 24 | 9/5 | ||
| 25 | 9/10 | ||
| 26 | 9/12 | ||
| 27 | 9/17 | ||
| 28 | 9/19 | ||
| 29 | 9/24 | ||
| 30 | 9/26 | ||
| 31 | 10/1 | ||
| 32 | 10/3 | Project Presentations |
Reading List
- Lecture 1:
- Lewyn, L.L.; Ytterdal, T.; Wulff, C.; Martin, K.; , “Analog Circuit Design in Nanoscale CMOS Technologies,” Proceedings of the IEEE , vol.97, no.10, pp.1687-1714, Oct. 2009 (URL)
- Dautriche, P.; , “Analog design trends and challenges in 28 and 20nm CMOS technology,” ESSCIRC (ESSCIRC), 2011 Proceedings of the , vol., no., pp.1-4, 12-16 Sept. 2011(URL)
- Lecture 2:
- Aparicio, R.; Hajimiri, A.; , “Capacity limits and matching properties of integrated capacitors ,” Solid-State Circuits, IEEE Journal of , vol.37, no.3, pp.384-393, Mar 2002 (URL)
- Lipka, B.; Yakun Zhang; Kleine, U.; , “Design of integrated matched resistors, capacitors and inductors,” Mixed Design of Integrated Circuits and Systems (MIXDES), 2010 Proceedings of the 17th International Conference , vol., no., pp.251-254, 24-26 June 2010 (URL)
- van der Wagt, J.P.A.; Chu, G.G.; Conrad, C.L.; , “A layout structure for matching many integrated resistors,” Circuits and Systems I: Regular Papers, IEEE Transactions on , vol.51, no.1, pp. 186- 190, Jan. 2004 (URL)
- Zhang, X.; Ni, B.; Mukhopadhyay, I.; Apsel, A. B.; , “Improving Absolute Accuracy of Integrated Resistors With Device Diversification,” Circuits and Systems II: Express Briefs, IEEE Transactions on , vol.PP, no.99, pp.1-5, 0 (URL)
- Lecture 3:
- Kinget, P.; Steyaert, M.; , “Impact of transistor mismatch on the speed-accuracy-power trade-off of analog CMOS circuits,” Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996 , vol., no., pp.333-336, 5-8 May 1996 (URL)
- Pelgrom, M.J.M.; Duinmaijer, A.C.J.; Welbers, A.P.G.; , “Matching properties of MOS transistors,” Solid-State Circuits, IEEE Journal of , vol.24, no.5, pp. 1433- 1439, Oct 1989 (URL)
- Pelgrom, M.J.M.; Tuinhout, H.P.; Vertregt, M.; , “Transistor matching in analog CMOS applications,” Electron Devices Meeting, 1998. IEDM ’98 Technical Digest., International , vol., no., pp.915-918, 6-9 Dec 1998 (URL)
References
- Gray, Hurst, Lewis, Meyer, Analysis & Design of Analog Integrated Circuits, Wiley 2001.
- Johns, Martin, Analog Integrated Circuit Design, Wiley 1997.