Class Information

Instructor

• Chris Vincent J. Densing
• E-mail: snapdensing@gmail.com, snap@eee.upd.edu.ph
• EEEI room 409

Schedule

• Lecture: Tuesdays 1-3PM, EEEI room 320
• Laboratory: Thursdays 1-4PM, EEE room 407

Announcements

• 5/27: There is a typo in the exam, problem 1. The rightmost combinational logic block should be labelled as CLC, and the example should be FFX-CLB-CLC-FFZ.
• 5/26: Final exam here
• 5/25: Final exam will be take home. You will have 24 hours to answer the exam and then submit it online through e-mail. The exam will be posted tomorrow, 5PM.
• 4/26: No class tomorrow. Standby for further announcements regarding the exam (I’ll post within the week).
• 3/5: Sorry for the confusion, but the exam is moved to March 17, NOT March 10. Ma’am Vion isn’t available on the 10th.
• 2/27: Hi guys, since I’m really busy here at Berkeley and Ma’am Vion won’t be available until March 10, let’s move the exam to March 10.
• 1/21: No lab class tomorrow. From now on, let’s assume that there will always be no lab class, unless otherwise stated here in the announcements section of the web page.
• 1/20: Welcome to EE 227!

Lecture Class Resources

• Course Outline
• Design Methodology
• Hardware Description Language I
• Hardware Description Language II
• MOS transistor basics
• MOS Combinational Circuits
• Logical Effort
• More on Logical Effort
• Interconnect
• Sequential Circuits
• SRAM
• Test

Laboratory Class Resources

• Lab Exercise: LCD Controller
• Design Problem
  • Overview on image compression
  • Detailed deliverables
  • Setup script for MATLAB with image processing
• Xilinx ISE tutorial
• Spartan 3E Starter Kit User Guide