This page gives the implementation details for the design problem on image compression.

Interface

The output image will be interfaced to a memory subsystem. The bitstream may also be interfaced to memory, or streamed from an external source through UART. The final decoded image will be displayed through a display driver, which reads pixel values from the output image memory subsystem.

If you opt to store the bitstream in memory, you may hardcode memory contents directly to the FPGA slices. However, this may result to large slice utilization. On the other hand, streaming through the UART interface will save slices, but will require you to design a UART controller for your system. You may decide freely on the packet format for streaming bitstream data through the UART.

The decoded image will be stored in memory, which we will refer to as image memory (IMEM). IMEM can be implemented using FPGA slices or the peripheral memory found in the Spartan 3E starter kit.

The display driver must be able to read from IMEM and display correct pixel values through the VGA port of the Spartan 3E starter kit.

Control signals for operating and debugging the decoder may also be included in your design. You are free to use any number of control signals as you deem necessary.

Deliverables

The decoder must be implemented in the Spartan 3E starter kit.

Each major process in decoding will merit points. The distribution of points and details for each are:

• 20% – Run-length decoding: completely decode an 8×8 block (Y_zig_dec).
• 10% – Reverse zig-zag scan: completely produce quantized QCIF image (Y_q_dec). Half points if process is performed on 8×8 block only.
• 20% – Inverse quantization: completely produce DCT QCIF image (Y_iq). Half points if process is performed on 8×8 block only.
• 25% – Inverse DCT: completely produce normalized decoded image (Y_dec_norm). Half points if process is performed on 8×8 block only.
• 5% – Complete image decoding: completely produce decoded image in correct scale (0-255).
• 10% – VGA display: completely produce decoded image and display it through VGA.
• 10% – UART bitstream input: stream input bitstream using UART

The bullets shown above, except for the UART bitstream input, are ladderized: in order to score the next bullet, you must be able to implement the previous one (perform the process on the 8×8 block level, or earn at least half of the points of the previous bullet). Take note that you do not need to perform each process for the whole QCIF image before moving on to the next one, since each 8×8 block is independent from one.

Verification

For partial verification, complete image decoding is the easiest process to verify since the values of the output are integers. In cases where the values are non-integers, you may use the internal number representation (determined by you) for representing the output. Just make sure to provide the necessary transformation (MATLAB code or something similar) when you have your design checked. Operations used for the transformation are limited to non-matrix operations. You will also be the one to provide the peripheral that automatically transfers/forwards outputs to a PC for verification purposes of partial designs. You may have to use an external peripheral (or the UART) to accomplish partial verification. Another alternative would be to use the VGA or LCD to display raw number values of the outputs of your intermediate processes.